Integrated circuits often contain memory elements. Memory elements may be based on cross-coupled inverters and may be used to store data. Each memory element may store a single bit of data.
Memory elements are often arranged in arrays. In a typical array, data lines are used to write data into the memory elements and are used to read data from the memory elements that have been loaded with data. Address lines may be used to select which of the memory elements are being accessed.
The memory elements may be configured in a dual-port arrangement. A conventional dual-port memory element includes a bi-stable latching circuit that stores a single bit of data (i.e., a latching circuit based on a pair of cross-coupled inverters). The latching circuit is connected to a write port (i.e., write data lines) through a set of write address transistors. The latching circuit is also connected to a read port (i.e., read data lines) through a set of read address transistors. The set of write address transistors are controlled by write address signals conveyed over a write address line, whereas the set of read address transistors are controlled by read address signals conveyed over a read address line. The read data lines are typically precharged to a high voltage value prior to read/write operations.
The conventional dual-port memory element may perform read operations using the read port and write operations using the write port. The read and write operations are controlled asynchronously using different address signals (i.e., read operations are controlled using read address signals, whereas write operations are controlled using write address signals). As a result, it is possible that the read address signal is high at the same time the write address signal is high during a write operation. This scenario in which the read port is enabled during a write operation may be referred to as a read-disturb write.
Enabling the read address transistors while the write address transistors are turned on may counteract the data loading process being performed by the write address transistors. Writing data in this way may undesirably increase the period of time that the write address signals are asserted to ensure proper loading of data. Asserting the write address signals for longer time periods limits the performance of the memory element.